1. Field of the Invention
The present invention relates to a data multiplexing and demultiplexing apparatus used in synchronous telecommunications.
2. Description of the Related Art
In the field of synchronous telecommunications systems such as an integrated services digital network (ISDN), synchronization bits and actual data are multiplexed for transmission. With data multiplexing-demultiplexing systems such as International Telecommunication Union (ITU) Standards H. 221 and H.223, data including synchronization data, audio data, video data and other data are multiplexed at a transmitter side and transmitted by way of one or more than one digital channels. At a receiver side, the multiplexed data are received and demultiplexed (separated) from each other according to the multiplexing system used at the transmitter side before they are distributed to respective decoding units for decoding the data.
A first prior art multiplexing and demultiplexing apparatus is constructed mainly by hardware (see: JP-A-4-207728). This will be explained later in detail.
In the first prior art multiplexing and demultiplexing apparatus, however, the protocol processing units have to be hierarchically configured. As a result, the hardware inevitably will become bulky. Additionally, if a new framing pattern is assigned, an extra state transition has to be added to a state machine, so that the time for responding a new protocol has to be modified to a large extent, and a number of work steps required for this modification will be by far longer.
A second prior art data multiplexing and demultiplexing apparatus is constructed mainly by software. This will also be explained later in detail.
The second prior art multiplexing and demultiplexing apparatus, however, is accompanied by the problem of involving many instruction cycles, which requires a highly efficient processor.